1. Field of the Invention
The present invention relates to a method for forming conductive wires of a semiconductor device, more particularly, to a method for forming conductive wires of a semiconductor device by utilizing a notching phenomenon of polycrystalline silicon.
2. Description of the Related Art
Semiconductor fabrication techniques attempt to attain high integration and high performance. Copper wiring is commonly used in the fabrication of semiconductor devices.
However, copper wires are difficult to etch using conventional etching materials. Due to this characteristic of copper wires, a damascene process is typically used in which an interlayer dielectric film is etched to form a trench, a copper layer is deposited to fill the trench, and the copper layer is then planarized.
There are various known methods for forming copper wires using the damascene process. For example, in one known process a trench is formed for the copper wire, and a via/contact hole is magnetically aligned.
Unfortunately, known methods have problems with lithography overlays, especially in semiconductor devices utilizing a design rule 0.13 μm. Using a design rule of 0.13 μm or below often results in misalignment of via/contact holes of up to 0.01 μm. It is difficult to control misalignment under 0.03 μm, especially using a stepper. The limit for misalignment for thickness uniformity of disposed layers and status of the stepper in a semiconductor device fabrication process is often greater than 0.07 μm. Thus, conventional damascene processes must be performed with many restrictions. In addition, the stepper itself has limits on overlays, since misalignment of the hole and the trench often occurs.
FIG. 1a is a cross sectional view illustrating a conventional process for forming a via/contact hole after forming a trench. First, a lower structure is formed at an upper portion of a semiconductor substrate 11. A first interlayer dielectric film 13 is formed on the whole surface of substrate 11. A lower metal wire mask, which exposes portions of substrate 11 for the lower metal wire, is used as an etching mask for etching the first interlayer dielectric film 13 to form a trench. A metal layer for wiring the lower metal is then formed on the surface of dielectric file 13 and an exposed portion of substrate 11. For example, a copper film may be used for the metal layer as a lower metal wire. The metal layer then undergoes a chemical mechanical polishing (“CMP”) process to form the lower metal wire 15.
A diffusion barrier layer 17 is formed on the whole surface having a predetermined thickness. The diffusion barrier layer 17 is typically a Si3N4 or SiC film. A second interlayer dielectric film 19 is then formed on top of the diffusion barrier layer 17.
An upper metal wire mask, which exposes portions for the upper metal wire, is used as the etching mask for etching the second interlayer dielectric film 19 based on a designated thickness and form a trench 23. A photoresist film pattern 21 is formed on the surface of the second interlayer dielectric film 19 to expose a location for the via/contact hole. However, because of misalignment, the photoresist film pattern 21 may be formed such that an upper portion of dielectric film 19 is exposed also.
FIG. 1b is a cross sectional view showing another conventional process of forming a via/contact hole after forming a trench. The same steps explained in FIG. 1a are repeated up to formation of the second interlayer dielectric film 19. Then, a via/contact mask is used as an etching mask for etching the second interlayer dielectric film 19 and form a via/contact hole 25. In addition, a photoresist film pattern 21 is formed on the second interlayer dielectric film 19 to expose portions for the upper metal wire. Occasionally, the lower metal wire 15 is not exposed, especially when the photoresist film pattern 21 is embedded into the via/contact hole 25, and the diffusion barrier layer 17 is not properly removed.
FIGS. 2a through 2c show the problems with the conventional processes for forming conductive wires in semiconductor devices. FIG. 2a shows the problems of using N2 or NH3 to remove the photoresist film pattern after the via/contact hole is formed. In particular, FIG. 2a shows a poisoning phenomenon in which acidic H− is produced in the exposed region of the photoresist film. During the process of forming the photoresist film pattern for the trench mask, acidic H+ may produced because of a reaction with an alkaline developing solution that is not properly dissolved or failed to become water (H2O). Instead, other remaining acidic ions in the via/contact hole, such as, NH+, NH2−, or NH3+, may cause the H− to remain undissolved and result in photoresist film in the shape of a mushroom.
FIG. 2b shows a dry etching process for forming the via/contact hole and the trench where no etching stop film is used in order to decrease parasitic permittivity between metal wires. As shown, the edge of the upper portion of the via/contact hole is collapsed due to a facet phenomenon, which is typically observed in the dry etching process.
FIG. 2c shows a trench etching process using the photoresist film pattern and embedding a part of the via/contact hole. As shown, a narrow gap between the via/contact hole and the trench causes etching byproducts that are produced by the trench etching process of the interlayer dielectric film to fill in the via/contact hole, and to attach to the photoresist film.
As explained above, traditional methods for forming conductive wires in semiconductor devices often cause misalignments during formation of the trench and the via/contact hole, and exhibits the problems shown in FIGS. 2a through 2c, i.e., poisoning, facet, and attachment of etching byproducts, which cause lower process yields and may lower reliability of the semiconductor device.
Accordingly, it would be desirable to provide methods, which overcome these and other shortcomings of the related art.